Field of the Invention
The invention relates to a method and a device for generating a reference voltage for discriminating the logic states of a data signal received in at least one receiver unit.
In every signal-transmitting system, be it a bidirectional or unidirectional system, a driver transmits a signal from a first point via a line or transmission link to a second point, where the signal is received. Equally, in a bidirectional system, a signal can be sent from the second point to the first point of the transmission link or of the transmission line, where it is likewise received and subsequently decoded. In the simplest case, a receiver unit forms the decoding of the signal in the form of a conversion depending on the logic state thereof into a level that is known in each case. To that end, the output of the receiver unit is switched back and forth between the two known signal levels, depending on whether or not the received signal level exceeds a specific threshold value (for example in the form of a reference voltage).
In prior art systems, the reference voltage Vref is typically generated outside a module and fed to the module and applied to the receiver units in the form of a predetermined voltage value. The value of the reference voltage is usually placed in the middle between the ideal highest value and lowest value of the received data signal, independently of the leading and trailing edges of the signal. However, there are a series of influencing variables which cause the reference voltage Vref to deviate from this mean value. Such deviations may be brought about by changes in the generated and received reference voltage itself and by the oscillation shape of the received data signals. By far the most frequent form of influence originates from deviations in the drivers which drive the data signals. In some systems, deviations are also brought about by the way in which the data signals are terminated. If the drivers of the data signals have an asymmetrical driver resistance for high and low levels and/or if the terminating resistance leads to an asymmetrical termination for high and low levels, the received data signal is not centered about its mean value, that is to say about the value of the generated reference voltage Vref. This leads to non-optimal temporal tolerances particularly in DDR memory systems, in which the data signals are expected to be completely symmetrical with regard to their leading and trailing edges.
It is accordingly an object of the invention to provide a method and a device for generating a reference voltage and for discriminating between logic states of a received data signal which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein the generated reference voltage leads to optimal signal time tolerances.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of generating a reference voltage, which comprises:
electrically transmitting a data signal and a continuous clock signal from a transmitting part to a receiving part;
the clock signal received at the receiving part being a continuous sequence of low and high clock signal states with a constant period duration, the clock signal received at the receiving part having low and high voltage levels corresponding to low and high levels of the data signal received at the receiving part, and the clock signal and the received data signal being subject to common system-governed electrical variations; and
integrating the clock signal at the receiver part during a specific time duration prior to receiving the data signal and generating the reference voltage from the clock signal at the receiving part.
In accordance with a primarily important aspect, therefore, the invention provides for a method for generating a reference voltage for discriminating the logic states of a received data signal. In addition to the data signal, a continuous clock signal is transmitted to the receiver end, which, at the receiver end, is a continuous sequence of low and high clock signal states with a constant period duration, and the reference voltage is generated from a time average of the low and high signal states of the clock at the receiver end. Specifically according to the invention:
the data signal and the clock signal are transmitted and received electrically;
the received clock signal has the same low and high voltage level as a received data signal and, in a manner governed by the system, is subjected to the same electrical variations as the received data signal; and
at the receiver end, an integration of the received clock signal is carried out during a specific time duration before the reception of the data signal.
The continuous clock signal which serves for generating the reference voltage has a constant pulse period duration and has a symmetrical sequence of low and high clock signal states, for example a clock signal pattern such as xe2x80x9c101010101010xe2x80x9d or xe2x80x9c1100110011001100xe2x80x9d etc. Situated on the module or chip which generates the reference voltage Vref from the clock signal is an integrator which integrates the received clock signal over a certain time duration before the reception of the data signal and, from this, generates the reference voltage adaptively to the changes in the data signal which are caused by the driver variations and terminating resistance variations.
With the above and other objects in view there is also provided, in accordance with the invention, a device for generating a reference voltage for discriminating between logic states of a data signal. The device comprises:
at least one receiver unit having an input for receiving the data signal and an input for receiving a continuous electrical clock signal formed of a sequence of low and high clock signal states;
the electrical clock signal and the electrical data signal received by said receiver unit having mutually corresponding low and high voltage levels and being subject to mutually corresponding system-governed electrical variations as the received data signal; and
an integrator for integrating the clock signal received at said receiver unit during a specific time duration prior to receiving the data signal and for generating the reference voltage from an integrated value of the clock signal.
In other words, in accordance with this second aspect of the invention, a device for generating a reference voltage for discriminating the logic states of a data signal received in at least one receiver unit, the receiver unit additionally being set up to receive a continuous clock signal as a sequence of low and high clock signal states and to form a reference voltage from a time average of the low and high signal states of the clock signal, is characterized by the following:
the received electrical clock signal has the same low and high voltage levels as the received electrical data signal and is subjected to the same system-governed electrical variations as the received data signal; and
the receiver unit has an integrator, which integrates the received clock signal during a specific time duration before the reception of the data signal and generates the reference voltage from an integrated value of said signal.
In a DDR-DRAM systemxe2x80x94serving as a system examplexe2x80x94which contains data signals DQ and data strobe signals DQS, the data strobe signal DQS is used as the additional clock signal for generating the reference voltage Vref since it is a clock signal which is subjected to the same system-governed variations as the received data signal DQ. If, as required, the integrator integrates the data strobe signal DQS for long enough before the data signal DQ is received, the reference voltage can be generated as a continuous value by the integrator. The reference voltage generated by the integrator ensures that the time duration during which the incoming data signal DQ lies above the reference voltage is just as long as the time duration during which the incoming data signal DQ lies below the reference voltage. This corresponds to a duty ratio of 50%.
It goes without saying that, in addition to the abovementioned DQS signal for the clock signal from which, according to the invention, the reference voltage is derived by integration, it is possible to use any other clock signal which meets the above conditions and can be integrated or averaged over a specific time duration.
In accordance with a concomitant feature of the invention, the clock signal and the data signal are driven with a common type, i.e., the same type of driver amplifier.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and device for generating a reference voltage, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.